The invention relates to apparatus and methods arbitrating bus contention conditions arising in a system wherein a first source has absolute priority in accessing a global RAM and other processors have lower priority access to the global RAM.
Digital signal processors such as the assignee's presently marketed SPV100 "adaptable signal processing board" provide programmable functions that allow high speed processing to accomplish various functions such as spectrum analysis, digital filtering, correlation convolution, and matrix inversion. The digital signal processing board is directly compatible with the popular "VME bus". Such products must operate at extremely high speed, and need to be as low in cost and size as possible. To this end, such products should provide optimized arbitrating of bus contention conditions between the VME bus, an internal microprocessor of the digital processing board, and an input/output port controller that is essentially a DMA (direct memory access) controller in order to permit high speed operation at relatively low cost. The SPV100 digital signal processing board requires a data memory and a separate I/O memory. This requirement increases the cost and complexity beyond what is desirable for the functionality achievable by use of that product. Furthermore, it is not possible for the VME bus to readily monitor the data memory, and the I/O memory is not readily accessable or monitorable by the internal microprocessor (a TMS32010) of the SPV100 digital processing board.
Although it is common to provide systems in which a common or global memory can be accessed by a plurality of separate processors, such systems generally have utilized either the technique of equally sharing access to the global memory, where in if one processor is accessing the global memory, the others cannot or else complex priority interrupt systems have been used that interrupt a low priority processor presently accessing the global memory and cause it to execute an interrupt subroutine and grant access to the global memory to the higher priority requesting processor. These techniques and the associated circuitry are so complex that they are not suitable in meeting the objective of providing a low cost, high speed digital signal processing board that can be plugged into a VME bus and accomplish rapid input and output of data to and from the digital signal processor board.